A Highly Efficient and Linear Broadband Common-Drain CMOS Power Amplifier With Transformer-Based Input-Matching Network

A broadband common-drain power amplifier (PA) with a transformer-based input matching network that is implemented in a 0.13 μm CMOS process is presented. This structure provides sufficient power gain along with high linearity and efficiency in comparison to other topologies. This is shown to be due to the low dependency of the power gain to the transistor transconductance and the smaller voltage variations across the gate-source capacitance. The proposed PA achieves an output 1 dB compression point of 11.5 dBm with a 3 dB bandwidth of 3.2 GHz, i.e., from 2.8 to 6 GHz. The PA has a 17.5 dB peak power gain and a 25% peak power-added efficiency at the 1 dB compression point. It occupies a 0.49 mm ² area.