Robust lateral double-diffused MOS with interleaved bulk and source for high-voltage electrostatic discharge protection

A device with bulk and source interleaved dotting is fabricated in a 0.5-μm 24 V CDMOS process, and the root cause of why it improves the multi-finger high-voltage lateral double-diffused MOS (LDMOS)´s electrostatic discharge (ESD) robustness is detected by Atlas three-dimensional device simulation and transmission line pulse system. Such device structure obtains strong ESD robustness by enlarging the intrinsic base resistance without increasing device area and sacrificing any ESD performance of nLDMOS. The measurement results demonstrated that, compared with traditional gate-grounded nLDMOS (GG-nLDMOS) with a total length of 400 μm, the proposed device can effectively raise the secondary breakdown current (I_t2) from 2.43 A up to 5.55 A, and enhance the ESD current discharge efficiency from 0.29 to 0.70 mA/μm².