• DocumentCode
    3611388
  • Title

    Clocking Wireline Systems: An Overview of Wireline Design Techniques

  • Author

    Casper, Bryan

  • Author_Institution
    PHY Res. Lab., Intel Labs., Hillsboro, OR, USA
  • Volume
    7
  • Issue
    4
  • fYear
    2015
  • Firstpage
    32
  • Lastpage
    41
  • Abstract
    Over the last several decades, digital communications technologies combined with integrated circuit scaling trends have enabled the microelectronic industry to dramatically scale the bandwidth of high-loss networks such as DSL and Ethernet. These channel-limited applications depend on sophisticated equalization techniques to push well beyond the uncompensated bandwidth of the system. And in the last two decades, short-distance wireline links used for chip-to-chip communication applications have enjoyed equally impressive data rate scaling??from a few hundred megabits per second per lane to multigigabits per second in products with volumes in the billions of units.
  • Keywords
    digital communication; digital subscriber lines; equalisers; local area networks; DSL; Ethernet; channel-limited applications; chip-to-chip communication; clocking wireline systems; data rate scaling; digital communications technologies; microelectronic industry; short-distance wireline links; wireline design techniques; Clocks; DSL; Digital filters; Integrated circuits; Jitter; Microelectronics; Oscillators; Phase locked loops; Thermal noise; Transmitters;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    1943-0582
  • Type

    jour

  • DOI
    10.1109/MSSC.2015.2476015
  • Filename
    7336656