• DocumentCode
    3611393
  • Title

    Minimum Power in Analog Amplifying Blocks: Presenting a Design Procedure

  • Author

    Sansen, Willy

  • Author_Institution
    KU Leuven, Leuven, Belgium
  • Volume
    7
  • Issue
    4
  • fYear
    2015
  • Firstpage
    83
  • Lastpage
    89
  • Abstract
    This tutorial presents a design procedure to establish such optimum power levels. It is developed for a single transistor. The BSIM6/EKV models are used as they greatly simplify this design procedure. and this is why they are discussed first in their shortest possible form. The next section gives the actual optimization procedure, which is then repeated for CMOS technologies down to 5 nm.
  • Keywords
    CMOS analogue integrated circuits; amplifiers; analogue circuits; BSIM6/EKV models; CMOS technology; analog amplifying blocks design procedure; minimum power; optimum power level; single transistor; CMOS integrated circuits; CMOS technology; Capacitance; Integrated circuit modeling; Semiconductor device modeling; Transistors;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits Magazine, IEEE
  • Publisher
    ieee
  • ISSN
    1943-0582
  • Type

    jour

  • DOI
    10.1109/MSSC.2015.2474237
  • Filename
    7336662
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3611393