Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

Author

Boruzdina, Anna B. ; Sogoyan, Armen V. ; Smolin, Anatoly A. ; Ulanova, Anastasia V. ; Gorbunov, Maxim S. ; Chumakov, Alexander I. ; Boychenko, Dmitry V.

Author_Institution

Specialized Electron. Syst. (SPELS), Nat. Res. Nucl. Univ. (NRNU) “MEPHI”, Moscow, Russia

Volume

62

Issue

6

fYear

2015

Firstpage

2860

Lastpage

2866

Abstract

The temperature dependence of single-event upset multiplicity in 65 nm CMOS SRAM was investigated in this paper. Experimental results show significant increase of upset multiplicity over a temperature range of 300 to 400 K. Main physical mechanisms leading to the increase of the multiplicity of upsets at elevated temperatures were studied using three-dimensional (3-D) device simulations. A major role of upset voltage decrease and temperature dependence of the parasitic bipolar effect was established. Simulation results can be used for maximal upset multiplicity estimation.

Keywords

CMOS memory circuits; SRAM chips; CMOS SRAM; maximal upset multiplicity estimation; parasitic bipolar effect; single-event upset multiplicity; size 65 nm; temperature dependence; upset voltage; CMOS integrated circuits; MOSFET; Random access memory; Sensitivity; Temperature dependence; Temperature sensors; Multiple bit upset (MBU); SRAM; multiple cell upset (MCU); temperature;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2015.2499120

Filename

7346523