High-Resolution Synthesizable Digitally-Controlled Delay Lines

Digitally-controlled delay lines (DCDLs) play a key role in timing distribution for trigger and data acquisition systems (TDAQ) of high energy Physics (HEP), where it is often necessary to add an open-loop fine-grained programmable phase delay to distributed clocks and/or data lines. In this work, we present the performance of DCDLs implemented according to an all-digital novel architecture. The architecture is completely technology-independent, it is described by means of a hardware description language and it can be placed and routed with automatic tools. Our solution is aimed at being used as a synthesizable block in FPGAs, as a proof-of-concept we implemented a prototype in a Xilinx Kintex-7 FPGA. We discuss the measured performance of the implemented delay line in terms of delay range, resolution and linearity. The logic utilization of the delay lines is also presented in the view of a scalable implementation.