DocumentCode

3612584

Title

Erratum: Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage

Volume

8

Issue

12

fYear

2015

Firstpage

2547

Lastpage

2547

fLanguage

English

Journal_Title

Power Electronics, IET

Publisher

iet

ISSN

1755-4535

Type

jour

DOI

10.1049/iet-pel.2015.0948

Filename

7364315