Title :
The CONNECT Network-on-Chip Generator
Author :
Papamichael, Michael K. ; Hoe, James C.
Abstract :
Efficiently supporting the communication needs of systems on chip with tens to hundreds of interacting modules requires a systematic and flexible network-on-chip (NoC) infrastructure. The freely available CONNECT generator lets users quickly navigate a range of design parameters to produce tailored NoC design instances in Verilog. To date, it has generated nearly 4,000 designs.
Keywords :
hardware description languages; network-on-chip; CONNECT generator; NoC design; Verilog; flexible NoC infrastructure; flexible network-on-chip infrastructure; network-on-chip generator; systematic NoC infrastructure; systematic network-on-chip infrastructure; Field programmable gate arrays; Hardware design languages; Network on chip; Network topology; Network-on-chip; Ports (Computers); Topology; IP blocks; NoC; SoC; Verilog; chip design; design synthesis; intellectual property; interconnect design; network on chip; scalable computing; system on chip;
DOI :
10.1109/MC.2015.378
