Title :
TSpice-Alecsis co-simulation
Author :
D. Stefanovic;M. Sokolovic;P. Petkovic;V. Litovski
Author_Institution :
Fac. of Electron. Eng., Nis Univ., Yugoslavia
fDate :
6/24/1905 12:00:00 AM
Abstract :
Tanner Tools system (TTS) is a very useful tool for design automation. However, during the layout verification phase, the overall circuit is flattened and only transistor level simulation by TSpice simulator is possible. Obviously, this is not convenient especially regarding large digital or mixed circuits. Therefore, this paper describes a methodology for joint simulation based on Alecsis mixed-mode circuit simulator. The method is described on example of 64-level Calibrated Current-steering DAC.
Keywords :
"Circuit simulation","Process design","Computational modeling","Speech synthesis","Layout","Design automation","Digital circuits","Libraries","Tuned circuits","Logic devices"
Conference_Titel :
Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Print_ISBN :
0-7803-7235-2
DOI :
10.1109/MIEL.2002.1003335
