Title :
Power analysis of multiplier blocks
Author :
S.S. Demirsoy;A.G. Dempster;I. Kale
Author_Institution :
Univ. of Westminster, London, UK
fDate :
6/24/1905 12:00:00 AM
Abstract :
In this study, three multiplier-blocks generated by different algorithms are analyzed for their power consumption via transition count based on their implementation on the Xilinx Virtex device. The high level Glitch-Path method, which is used for estimating the relative figures of transitions occurring at the outputs of the adders, has been refined for more accurate estimation and a new method GP Score is proposed. Several design issues are discussed regarding ways of reducing the transitions.
Keywords :
"Adders","Energy consumption","Finite impulse response filter","Power generation","Clocks","Algorithm design and analysis","Digital filters","Costs","CMOS digital integrated circuits","Power dissipation"
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1009836
