Two-dimensional signal gating for low-power array multiplier design

Two-dimensional (2-D) signal gating schemes are proposed for low-power array multiplier design. 2-D gating provides gating lines for both multiplicand and multiplier operands. Different regions of the multiplier are dynamically deactivated according to the actual precision of each operand. Bit-level implementation is studied in order to minimize the gating overhead and make a realistic evaluation. Compared to previous work, the 2-D signal gating is better in terms of power consumption, power-delay product and power-area product.