3613608

Variable partitioning and scheduling of multiple memory architectures for DSP

Q. Zhuge;B. Xiao;E.H.-M. Sha

2002

6/24/1905 12:00:00 AM

"Memory architecture","Digital signal processing","Optimal scheduling","Bandwidth","Processor scheduling","Computer architecture","Computer science","Partitioning algorithms","Scheduling algorithm","Pipeline processing"

ieee

Parallel and Distributed Processing Symposium., Proceedings International, IPDPS 2002, Abstracts and CD-ROM

0-7695-1573-8

conf

10.1109/IPDPS.2002.1016516

1016516