DocumentCode
3613924
Title
Fine-grain CAM-tag cache resizing using miss tags
Author
M. Zhang;K. Asanovic
Author_Institution
Lab. for Comput. Sci., MIT, Cambridge, MA, USA
fYear
2002
fDate
6/24/1905 12:00:00 AM
Firstpage
130
Lastpage
135
Abstract
A new dynamic cache resizing scheme for low-power CAM (content addressable memory)-tag caches is introduced. A control algorithm that is only activated on cache misses uses a duplicate set of tags, the miss tags, to minimize active cache size while sustaining close to the same hit rate as a full size cache. The cache partitioning mechanism saves both switching and leakage energy in unused partitions with little impact on cycle time. Simulation results show that the scheme saves 28-56% of data cache energy and 34-49% of instruction cache energy with minimal performance impact.
Keywords
"Technical Activities Guide -TAG","Laboratories","Computer science","Size control","Leakage current","Microprocessors","Energy consumption","Permission","Partitioning algorithms","Cache memory"
Publisher
ieee
Conference_Titel
Low Power Electronics and Design, 2002. ISLPED ´02. Proceedings of the 2002 International Symposium on
Print_ISBN
1-5811-3475-4
Type
conf
DOI
10.1109/LPE.2002.146725
Filename
1029575
Link To Document