Title :
Static series-voltage noise margins of CBL, CSL and CMOS
Author :
A. Szabo;Z. Butkovic
Author_Institution :
Fac. of Electr. Eng. & Comput., Zagreb Univ., Croatia
fDate :
6/24/1905 12:00:00 AM
Abstract :
The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in a system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (current-balanced logic), CSL (current-steering logic) and CMOS are determined and compared.
Keywords :
"CMOS logic circuits","Flip-flops","Circuit noise","Logic circuits","Voltage","Integrated circuit noise","Semiconductor device noise","Logic gates","Pulse inverters","Logic devices"
Conference_Titel :
Electronics, Circuits and Systems, 2002. 9th International Conference on
Print_ISBN :
0-7803-7596-3
DOI :
10.1109/ICECS.2002.1046236
