The design of a new wideband and low-power CMOS active polyphase filter for low-IF receiver applications

This work presents a new technique to implement an active polyphase filter. In this design, the currents mirrored from capacitors and transistors realize the high-pass and low-pass signals, respectively. The multi-stage structure, which is commonly used in RC networks, expands the frequency bandwidth. Furthermore, a constant-gm bias circuit is used to decrease the sensitivities of gain and bandwidth to temperature and process variations. HSPICE is simulated to confirm the performances. The voltage gain is 8.1 dB and THD is -48 dB when a 20 MHz, 100 mV quadrature signal is applied. The image-rejection ratio exceeds 60 dB over the frequency range of 15.4 MHz /spl sim/ 44.6 MHz. The polyphase filter is implemented with 0.18 /spl mu/m CMOS technology and the power dissipation is 6.85 mW with a 1.8 V power supply. Simulations of various corners and temperatures show that the variations in gain and frequency are effectively controlled.