A methodology for designing communication architectures for multiprocessor SoCs

Multiprocessor SoCs (MSoCs) for network and stream processing have to cope with growing speed and flexibility requirements of new complex packet processing tasks. Performance optimization of a homogenous network of CPUs in a certain application leads basically to optimization of CPUs interconnect and communication algorithms. Several on-chip communication architectures are compared with respect to their cost, simplicity of routing algorithms, and performance in collective communications. It is shown, that if group communication patterns are considered in certain proportions, the fat cube architecture rather than Octagonal architecture may have the best performance/cost figure. A methodology for designing efficient on-chip interconnects on regular group communication patterns is suggested. It may be useful if the system is targeted for specific class of applications.