Title :
Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip
Author :
E. Rijpkema;K.G.W. Goossens;A. Radulescu;J. Dielissen;J. van Meerbergen;P. Wielage;E. Waterlander
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
fDate :
6/25/1905 12:00:00 AM
Abstract :
Managing the complexity of designing chips containing billions of transistors requires decoupling computation from communication. For the communication, scalable and compositional interconnects, such as networks on chip (NoC) must be used. In this paper, we show that guaranteed services are essential in achieving this decoupling. Guarantees typically come at the cost of lower resource utilization. To avoid this, they must be used in combination with best-effort services. The key element of our NoC is a router consisting conceptually of two parts: the so-called guaranteed throughput (GT) and best-effort (BE) routers. We combine the GT and BE router architectures in an efficient implementation by sharing resources. We show the trade offs between hardware complexity and efficiency of the combined router, and the motivation of our choices. Our reasoning for the trade offs is validated with a prototype router implementation. We show a lay-out of an input-queued wormhole 5/spl times/5 router with an aggregate bandwidth of 80 Gbit/s. It occupies 0.26 mm/sup 2/ in CMOS12. This shows that our router provides high performance at reasonable cost, bringing NoCs one step closer.
Keywords :
"Intelligent networks","Network-on-a-chip","Costs","Hardware","Prototypes","Aggregates","Bandwidth","Technology management","Wires","Laboratories"
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2003
Print_ISBN :
0-7695-1870-2
DOI :
10.1109/DATE.2003.1253633