A gate leakage reduction strategy for future CMOS circuits

We show that a technique previously introduced for sub-threshold leakage reduction can be effectively used to reduce gate leakage dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunnelling currents that contributes to gate leakage power dissipation in future CMOS circuits.