DocumentCode :
3615106
Title :
Are our design for testability features fault secure?
Author :
C. Metra;T.M. Mak;M. Omana
Author_Institution :
DEIS, Bologna Univ., Italy
Volume :
1
fYear :
2004
fDate :
6/26/1905 12:00:00 AM
Firstpage :
714
Abstract :
We analyze the risks associated with faults affecting some common design for testability (DFT) features employed within digital products. We will show that some DFT structures may become useless, with consequent dramatic impact on test effectiveness and product quality. We borrow the fault secure property and we will show that it guarantees that no escapes or false acceptance of faulty products may occur because of faults within the DFT structures.
Keywords :
"Design for testability","Circuit faults","Circuit testing","Built-in self-test","Fault detection","Design for disassembly","Flip-flops","Risk analysis","Microelectronics","Silicon"
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings
ISSN :
1530-1591
Print_ISBN :
0-7695-2085-5
Type :
conf
DOI :
10.1109/DATE.2004.1268944
Filename :
1268944
Link To Document :
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