مرکز منطقه ای اطلاع رساني علوم و فناوري

DocumentCode :

3615397

Title :

Infrastructure IP for SOC

Author :

Y. Zorian

Author_Institution :

Virage Logic

fYear :

2004

fDate :

6/26/1905 12:00:00 AM

Keywords :

"Manufacturing","Logic testing","Design engineering","Logic design","Design for testability","Design optimization","Feeds"

Publisher :

ieee

Conference_Titel :

VLSI Test Symposium, 2004. Proceedings. 22nd IEEE

ISSN :

1093-0167

Print_ISBN :

0-7695-2134-7

Type :

conf

DOI :

10.1109/VTEST.2004.1299213

Filename :

1299213

Link To Document :