Design flow for automated programming of FPGA

Today complex systems are modeled on a high level of abstraction by including functional and architectural description as well as environmental components. The system is specified on mission level and such an overall model is simulated together with operational conditions. The design flow from mission level to programming of FPGA chips is presented in this paper. In order to automate transition from mission/operational to implementation level models used in FPGA synthesis tools, a VHDL code generator for finite state machine modules is developed. The generator structure and conversion process are presented in more detail.