Generation of factorized symbolic network function by circuit topology reduction

This paper introduces a symbolic analysis method for network function generation in nested form. The method utilises an original circuit topology graph. The network function construction implies visiting vertices of the graph in bottom-up order. There is no need to build circuit matrix and solve circuit equations. This makes the method very efficient. It is implemented on Miller-compensated CMOS operational transconductance amplifier. Obtained network function has very compact form suitable for postprocessing calculations.