• DocumentCode
    3615675
  • Title

    Incremental satisfiability counting for real-time systems

  • Author

    S. Andrei;W.-N. Chin

  • Author_Institution
    Singapore-MIT Alliance, Nat. Univ. of Singapore, Singapore
  • fYear
    2004
  • fDate
    6/26/1905 12:00:00 AM
  • Firstpage
    482
  • Lastpage
    489
  • Abstract
    Testing constraints for real-time systems are usually verified through the satisfiability of propositional formulae. In this paper, we propose an alternative where the verification of timing constraints can be done by counting the number of truth assignments instead of Boolean satisfiability. This number can also tell us how "far away" a given specification is from satisfying its safety assertion. Furthermore, specifications and safety assertions are often modified in an incremental fashion, where problematic bugs are fixed one at a time. To support this development, we propose an incremental algorithm for counting satisfiability. Our proposed incremental algorithm is optimal as no unnecessary nodes are created during each counting. This works for the class of expressions, known as path RTL ([F. Jahanian et al. (1987), F. Wang et al. (1994)]). To illustrate this application, we show how incremental satisfiability counting can be applied to a well-known rail-road crossing example, particularly when its specification is still being refined.
  • Keywords
    "Real time systems","Safety","Timing","Debugging","Arithmetic","Logic","Computer science","System testing","Computer bugs","Costs"
  • Publisher
    ieee
  • Conference_Titel
    Real-Time and Embedded Technology and Applications Symposium, 2004. Proceedings. RTAS 2004. 10th IEEE
  • ISSN
    1545-3421
  • Print_ISBN
    0-7695-2148-7
  • Type

    conf

  • DOI
    10.1109/RTTAS.2004.1317295
  • Filename
    1317295