Low-area on-chip circuit for jitter measurement in a phase-locked loop

In this paper we propose a novel on-chip circuit to measure the jitter present at the output of phase-locked-loops (PLLs) used for synthesizing a clock with equal or higher frequency than the input clock. This measure is performed at every period of the PLL reference clock. The obtained digital outputs are encoded by means of a thermometer code. Our proposed circuit is able to measure the jitter of PLLs, providing an output frequency in the GHz range. Compared to other available techniques, that proposed here requires lower cost in terms of area overhead (implying an increase in PLL area <4%) and circuit complexity, while featuring comparable accuracy and test time.