DocumentCode :
3615754
Title :
Integrating a single physical verification tool for systems-on-chip designs
Author :
J. Paris
fYear :
2004
fDate :
6/26/1905 12:00:00 AM
Firstpage :
7
Lastpage :
7
Keywords :
"Design engineering","Design automation","Layout","Application specific integrated circuits","Signal processing","Signal design","Libraries","Robustness","Costs","Graphics"
Publisher :
ieee
Conference_Titel :
System-on-Chip for Real-Time Applications, 2004.Proceedings. 4th IEEE International Workshop on
Print_ISBN :
0-7695-2182-7
Type :
conf
DOI :
10.1109/IWSOC.2004.1319839
Filename :
1319839
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3615754
