Asynchronous multi-core architecture for level set methods

The paper proposes an asynchronous multi-core architecture for embedded systems using partial differential equation-based image processing algorithms. A study of data flow and timing analysis is carried out in order to reveal optimal global architecture specifications. The global architecture uses a semi-parallel approach with several processing units running in parallel and shared memory blocks. The results are illustrated by the implementation of a continuous watershed transform, followed by a discussion of the measured execution time and the computational load to demonstrate the efficiency.