Low power-four quadrant CMOS analog multiplier for artificial neural networks

Artificial neural networks (ANN) consist of many neuron and synapse subcircuits which are massively parallel processing elements. The number of transistors and the power consumption of circuits with many synapses are important performance criteria in ANN applications. Analog multipliers have a great importance in analog signal processing. With their specifications of density, speed and low power consumption, they are used in the electronic realization of artificial neural networks. A low power (133 /spl mu/W), four quadrant analog multiplier with a low transistor count is proposed, particularly for artificial neural network applications. The circuit was designed using 1.5 /spl mu/m Tu/spl uml/bitak-Yital process parameters. The power supply of the circuit is /spl plusmn/5 V. The linear dynamic range of inputs is /spl plusmn/1 V.