DocumentCode :
3616331
Title :
Signal integrity verification using high speed monitors
Author :
V. Avendano;V. Champac;J. Figueras
Author_Institution :
National Institute for Astrophysics
fYear :
2004
fDate :
6/26/1905 12:00:00 AM
Firstpage :
114
Lastpage :
119
Keywords :
"Integrated circuit interconnections","Voltage","Circuit simulation","Logic devices","Delay estimation","Pins","Integrated circuit technology","Integrated circuit noise","Crosstalk","Noise level"
Publisher :
ieee
Conference_Titel :
Test Symposium, 2004. ETS 2004. Proceedings. Ninth IEEE European
Print_ISBN :
0-7695-2119-3
Type :
conf
DOI :
10.1109/ETSYM.2004.1347622
Filename :
1347622
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=3616331
