Stability of the fast voltage control loop in power factor correctors

This paper introduces a new method for stability analysis and design of a fast voltage loop in rectifiers with power factor correction (PFC). The method is based on the circle criterion, which unifies tools for nonlinear system analysis with frequency domain analysis tools used in linear systems. The controller design procedure is demonstrated and experimentally verified on two experimental systems that are built around a 300 W digitally-controlled boost-based PFC. In the first system, the expansion of the voltage loop bandwidth is allowed by introduction of a self-tuning comb filter (STCF) for the output voltage ripple elimination. In the second experimental set-up, the fast voltage loop is enabled through utilization of a "dead-zone" in analog-to-digital conversion.