DocumentCode :
3618553
Title :
Accelerating Multiprocessor Simulation with a Memory Timestamp Record
Author :
K.C. Barr;H. Pan;M. Zhang;K. Asanovic
Author_Institution :
Comput. Sci. & Artificial Intelligence Lab., MIT, Cambridge, MA
fYear :
2005
fDate :
6/27/1905 12:00:00 AM
Firstpage :
66
Lastpage :
77
Abstract :
We introduce a fast and accurate technique for initializing the directory and cache state of a multiprocessor system based on a novel software structure called the memory timestamp record (MTR). The MTR is a versatile, compressed snapshot of memory reference patterns which can be rapidly updated during fast-forwarded simulation, or stored as part of a checkpoint. We evaluate MTR using a full-system simulation of a directory-based cache-coherent multiprocessor running a range of multithreaded workloads. Both MTR and a multiprocessor version of functional fast-forwarding (FFW) make similar performance estimates, usually within 15% of our detailed model. In addition to other benefits, we show that MTR has up to a 1.45x speedup over FFW, and a 7.7x speedup over our detailed baseline
Keywords :
"Acceleration","Microarchitecture","Computational modeling","Sampling methods","Multiprocessing systems","Checkpointing","Predictive models","Computer science","Artificial intelligence","Laboratories"
Publisher :
ieee
Conference_Titel :
Performance Analysis of Systems and Software, 2005. ISPASS 2005. IEEE International Symposium on
Print_ISBN :
0-7803-8965-4
Type :
conf
DOI :
10.1109/ISPASS.2005.1430560
Filename :
1430560
Link To Document :
بازگشت