• DocumentCode
    3619161
  • Title

    An 8-bit 13-Msamples/s digital-background-calibrated algorithmic ADC

  • Author

    E.B. Blecker;O.E. Erdogan;P.J. Hurst;S.H. Lewis

  • Author_Institution
    University of California, Davis, CA
  • fYear
    2000
  • fDate
    6/22/1905 12:00:00 AM
  • Firstpage
    180
  • Lastpage
    183
  • Abstract
    An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit 2-stage pipelined algorithmic analog-to-digital converter. At a sampling rate of 13 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic range (SFDR) is 60 dB. The total power dissipation is 23 mW from 3.0V. The active analog area is 0.11 mm2. The digital calibration is implemented off chip.
  • Keywords
    "Calibration","Erbium","Sampling methods","Analog-digital conversion","Operational amplifiers","Timing","Solid state circuits","Laboratories","Tellurium","Pipelines"
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2000. ESSCIRC ´00. Proceedings of the 26rd European
  • Type

    conf

  • Filename
    1471241
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3619161