• DocumentCode
    3619168
  • Title

    500 Mb/s soft output Viterbi decoder

  • Author

    Engling Yeo;S. Augsburger;Wm.R. Davis;B. Nikolic

  • Author_Institution
    University of California, Berkeley, CA
  • fYear
    2002
  • fDate
    6/24/1905 12:00:00 AM
  • Firstpage
    523
  • Lastpage
    526
  • Abstract
    Two 8-state, 7-bit soft output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in 0.18µm CMOS technology. Architectural transformation of the add-compare-select structures and modification of the register exchange allow a high throughput with small area overhead. The 4mm2chip has been verified to decode at 500Mb/s with 1.8V supply. These decoders are used with Turbo codes, which have been demonstrated to achieve information rates very close to the Shannon limit.
  • Keywords
    "Viterbi algorithm","Convolutional codes","Throughput","CMOS technology","Registers","Turbo codes","Iterative decoding","Computer architecture","Impedance matching","Information rates"
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2002. ESSCIRC 2002. Proceedings of the 28th European
  • Type

    conf

  • Filename
    1471580
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3619168