FPGA implemented decimating filter

This paper describes the synthesis and the implementation of a digital decimating filter for an ultrasonic beamformer, which uses delta sigma modulators to acquire the received ultrasonic signals. For conventional ultrasonic imaging systems this high-order filter can be very long and complicated and consume a fair amount of power because only one such filter is required per beam sum. Portable ultrasonic imaging systems require on-chip implemented receive beamformer. Various MATLAB scripts have been written to aid filter design and to analyze functionality and performance. A hardware simulation for the digital decimating filter is introduced and its performance is verified by a dedicated MATLAB simulation. The system is implemented by FPGA technology (ALTERA 10K series) and the simulation confirm the system´s performances