• DocumentCode
    3619517
  • Title

    Optimisation of a TiSi2 SALICIDE Process in a 0.18 um CMOS Technology with Dual Selective Etch Process TISE2

  • Author

    G. Pares;M.-T. Basso;S. Rayr;M. Haond

  • Author_Institution
    STMicroelectronics, Crolles, France
  • fYear
    2000
  • fDate
    6/22/1905 12:00:00 AM
  • Firstpage
    256
  • Lastpage
    259
  • Keywords
    "CMOS technology","CMOS process","Etching","Tin","Tellurium","Thermal resistance","Silicides","Chemistry","Electrical resistance measurement","Hafnium"
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 2000. Proceeding of the 30th European
  • Print_ISBN
    2-86332-248-6
  • Type

    conf

  • DOI
    10.1109/ESSDERC.2000.194763
  • Filename
    1503693
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3619517