DocumentCode
3619662
Title
Control gate patterning optimisation for improved yield of 0.18um embedded FLASH technology
Author
M. Hendriks;E. Gerritsen;D. Dormans
Author_Institution
Philips Semiconductors, Nijmegen, The Netherlands
fYear
2001
fDate
6/23/1905 12:00:00 AM
Firstpage
387
Lastpage
390
Keywords
"Etching","Character generation","Nonvolatile memory","Fabrication","Isolation technology","Manufacturing","Size control","Low voltage","Dielectrics","Iron"
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 2001. Proceeding of the 31st European
Print_ISBN
2-914601-01-8
Type
conf
DOI
10.1109/ESSDERC.2001.195282
Filename
1506664
Link To Document