• DocumentCode
    3619689
  • Title

    Automatic discovery of RTL benchmark circuits with predefined testability properties

  • Author

    T. Pecenka;Z. Kotasek;L. Sekanina;J. Strnadel

  • Author_Institution
    Fac. of Inf. Technol., Brno Univ. of Technol., Czech Republic
  • fYear
    2005
  • fDate
    6/27/1905 12:00:00 AM
  • Firstpage
    51
  • Lastpage
    58
  • Abstract
    The paper describes the utilization of evolutionary algorithms for automatic discovery of benchmark circuits. The main objective of the paper is to show that relatively large and complex (benchmark) circuits can be evolved in case that only a given property (e.g. testability) is required and the function of the circuit is not considered. This principle is demonstrated on automatic discovery of benchmark circuits with predefined structural and diagnostic properties. Fitness evaluation for the proposed algorithm is based on testability analysis with linear time complexity. During the evolution, the solutions which are refused to be synthesized by a design system are excluded from the process of developing a new generation of benchmark circuits. The evolved circuits contain thousands of components and satisfy the required testability properties.
  • Keywords
    "Circuit testing","Benchmark testing","Automatic testing","Circuit synthesis","Evolutionary computation","Digital circuits","Vectors","Controllability","Observability","Information technology"
  • Publisher
    ieee
  • Conference_Titel
    Evolvable Hardware, 2005. Proceedings. 2005 NASA/DoD Conference on
  • ISSN
    1550-6029
  • Print_ISBN
    0-7695-2399-4
  • Type

    conf

  • DOI
    10.1109/EH.2005.10
  • Filename
    1508481