FIGARO - an automatic tool flow for designs with dynamic reconfiguration

Although runtime partial dynamic reconfiguration of FPGAs has been researched for many years and there have been a few FPGAs equipped with the required architectural features, it has yet to achieve general recognition by the commercial design community. This is mainly due to the lack of a professional CAD tool support. This paper presents extended concepts from E. L. Horta et al. (2002), Xilinx Application Note 290 (2004) and I. Robertson et al. (2002) implemented in a placement and routing tool. The tool supports creation of partially dynamically reconfigurable designs from input EDIF files and user-specified reconfiguration schedule down to bitstream generation for FPGAs that support this technology, such as the Atmel AT40K and AT94K series.