A flexible architecture for image reconstruction in H.264/AVC decoders

The H.264/AVC is the most recent standard of video compression. In this paper original and flexible architecture of image reconstruction block for H.264/AVC decoder is presented. Depending on application requirements the proposed design may be configured as low complexity simple unit with good performance or as fully pipelined construction with high performance. The architecture was implemented in Verilog HDL and synthesized and then tested on Xilinx VirtexII family device. The simulation results indicate that the implemented circuit is capable to process real-time video at clock close to the image sampling frequency.