Will continued process-node shrinks kill high-performance analog design?

Author

J. Savoj;D. RIch;B. Forejt;P. Kinget; Un-Ku Moon;M. Oprysko;B. Razavi;H. Shichijo;A. Wang

fYear

2005

fDate

6/27/1905 12:00:00 AM

Firstpage

616

Lastpage

617

Keywords

"Instruments","Moon","Circuits","Sampling methods","Phase locked loops","Voltage fluctuations","Clocks"

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2005. Proceedings of the IEEE 2005

Print_ISBN

0-7803-9023-7

Type

DOI

10.1109/CICC.2005.1568744

Filename

1568744

Link To Document