DocumentCode :
3620973
Title :
Yield of VLSI Circuits: Myths vs. Reality
Author :
A.J. Strojwas
Author_Institution :
Department of Electrical and Computer Engineering, Carnegie-Mellon University, Pittsburgh, PA
fYear :
1986
fDate :
6/8/1905 12:00:00 AM
Firstpage :
234
Lastpage :
235
Keywords :
"Very large scale integration","Integrated circuit modeling","Predictive models","Manufacturing processes","Process design","Integrated circuit layout","Computer aided manufacturing","Virtual manufacturing","Process control","Fabrication"
Publisher :
ieee
Conference_Titel :
Design Automation, 1986. 23rd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0702-5
Type :
conf
DOI :
10.1109/DAC.1986.1586094
Filename :
1586094
Link To Document :
بازگشت