A CMOS programmable routing architecture

The design of a programmable interconnection cell and a more complex routing architecture based on this cell are described. The cell can be used for interconnecting inputs and outputs of blocks that can implement any logic function. The connections are made by means of vertical and horizontal lines. The core of this programmable cell is based on transmission gates. With the routing architecture, interconnections among 15 vertical and 12 horizontal lines can be made. Both circuits have been designed at mask level using CMOS technology of 2 mu m and two metals.