High order FIR digital filter realization in distributed arithmetic

For FIR digital filters implemented in distributed arithmetic, the exponential growth of the memory size with the impulse response coefficients has always been considered to be a fundamental drawback of implementation. With higher-order section cascade structures it is possible to reduce the memory size requirements at the same speed of operation as in the basic distributed arithmetic implementation, since no additional adders are needed. The simulated results for frequency response calculations with stopband attenuation, passband gain, and passband ripple are presented for several digital filters.