• DocumentCode
    3621877
  • Title

    New Aspects in HDL´s Performance Evaluation

  • Author

    B. Andelkovic;V. Litovski;V. Zerbe

  • Author_Institution
    Faculty of Electronic Engineering, University of Niš
  • Volume
    1
  • fYear
    2005
  • fDate
    6/27/1905 12:00:00 AM
  • Firstpage
    499
  • Lastpage
    502
  • Abstract
    New aspects in hardware description language´s (HDL) performance evaluation such as object-orientation, system-level modeling, analog and mixed-signal modeling, software description and verification capabilities are analyzed in this paper. Features of mainstream HDLs and verification languages VHDL-AMS, Java, SystemC, AleC++, MLDesigner, Open Vera, the e language, PSL and SystemVerilog are compared in the context of these aspects
  • Keywords
    "Hardware design languages","Object oriented modeling","Java","System-on-a-chip","Counting circuits","Software performance","Frequency domain analysis","Yarn","Performance analysis","Power system modeling"
  • Publisher
    ieee
  • Conference_Titel
    Computer as a Tool, 2005. EUROCON 2005.The International Conference on
  • Print_ISBN
    1-4244-0049-X
  • Type

    conf

  • DOI
    10.1109/EURCON.2005.1629974
  • Filename
    1629974
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3621877