Compact MAC Architecture of FIR Filters in Solid-State Energy Meter

This paper presents compact MAC (multiplier and accumulator) architecture of digital FIR filters applied in a solid-state energy meter. Comparing to other architectures, the proposed compact MAC architecture has smaller chip area, decreases power dissipation and optimizes speed. Implementation of basic building blocks of the architecture is described. The filter architectures are coded in VHDL, verified by simulations and synthesized using AMI semiconductor CMOS 0.35 mum standard cell library