DocumentCode
3621953
Title
BIST Structure for ASIC Circuits
Author
I. Gosciniak
Author_Institution
University of Silesia in Katowice, Poland
Volume
1
fYear
2005
fDate
6/27/1905 12:00:00 AM
Firstpage
840
Lastpage
845
Abstract
The paper presents the possibility to use linear modification to build the testing structure for the ASIC SC and GA mask programmable circuits. The proposed conception was verified by simulating research of proposed testing structure using ISCAS´89 benchmark circuits. The conclusions included in the paper were illustrated by simulating research results of single and multimodular circuits. The proposed method of linear modification is characterised by small circuit overhead and high effectiveness of testing
Keywords
"Built-in self-test","Application specific integrated circuits","Circuit testing","Automatic testing","Buildings","Registers","Genetic algorithms","Logic testing","Benchmark testing","Feedback"
Publisher
ieee
Conference_Titel
Computational Intelligence for Modelling, Control and Automation, 2005 and International Conference on Intelligent Agents, Web Technologies and Internet Commerce, International Conference on
Print_ISBN
0-7695-2504-0
Type
conf
DOI
10.1109/CIMCA.2005.1631369
Filename
1631369
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