Title :
Fault tolerant system design method based on self-checking circuits
Author :
P. Kubalik;P. Fiser;H. Kubatova
Author_Institution :
Dept. of Comput. Sci. & Eng., Czech Tech. Univ., Prague, Czech Republic
fDate :
6/28/1905 12:00:00 AM
Abstract :
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults
Keywords :
"Fault tolerant systems","Design methodology","Field programmable gate arrays","Circuit faults","Single event transient","Minimization","Input variables","Computer science","Reliability engineering","Design engineering"
Conference_Titel :
On-Line Testing Symposium, 2006. IOLTS 2006. 12th IEEE International
Print_ISBN :
0-7695-2620-9
DOI :
10.1109/IOLTS.2006.37
