Title :
Synthesis of high-performance packet processing pipelines
Author :
C. Soviani;I. Hadzic;S.A. Edwards
Author_Institution :
CS Dept., Columbia Univ., New York, NY, USA
fDate :
6/28/1905 12:00:00 AM
Abstract :
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We propose a high-level synthesis technique for a new model for representing packet editing functions. Experiments show our circuits achieve a throughput of up to 40Gb/s on a commercially available FPGA device, equal to state-of-the-art implementations
Keywords :
"Pipelines","Switches","Packet switching","Circuits","Field programmable gate arrays","Traffic control","High level synthesis","Hardware","Throughput","Fabrics"
Conference_Titel :
Design Automation Conference, 2006 43rd ACM/IEEE
Print_ISBN :
1-59593-381-6
DOI :
10.1145/1146909.1147081