DocumentCode :
3622564
Title :
Dual-Mode Quadruple Precision Floating-Point Adder
Author :
A. Akkas
Author_Institution :
Koc University, Turkey
fYear :
2006
fDate :
6/28/1905 12:00:00 AM
Firstpage :
211
Lastpage :
220
Abstract :
Many scientific applications require more accurate computations than double precision or double-extended precision floating-point arithmetic. This paper presents a dual-mode quadruple precision floating-point adder that also supports two parallel double precision additions. A technique and modifications used to design the dual-mode quadruple precision adder are also applied to implement a dual-mode double precision adder, which supports one double precision and two parallel single precision operations. To estimate area and worst case delay, the conventional and the dual-mode double and quadruple precision adders are implemented in VHDL and synthesized. The correctness of all the designs is also tested and verified through extensive simulation. Synthesis results show that the dual-mode quadruple precision adder requires roughly 14% more area than the conventional quadruple precision adder and a worst case delay is 9% longer
Keywords :
"Floating-point arithmetic","Hardware","Application software","Computational modeling","Algorithm design and analysis","Delay estimation","Physics computing","Microprocessors","Testing","Digital arithmetic"
Publisher :
ieee
Conference_Titel :
Digital System Design: Architectures, Methods and Tools, 2006. DSD 2006. 9th EUROMICRO Conference on
Print_ISBN :
0-7695-2609-8
Type :
conf
DOI :
10.1109/DSD.2006.47
Filename :
1690042
Link To Document :
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