Effects of charge-based computation non-idealities on CMOS image compression sensors

We present a CMOS image sensor that performs focal plane image decomposition based on charge sharing computation circuitry. The effect of parasitic capacitance between capacitor bottom plate and substrate on the computational accuracy is discussed and a new circuit is also proposed to characterize the parasitic effects. The test results demonstrate that prediction based focal plane image compression can be realized inside the sensor array resulting in high compression performance using frame rate pixel parallel computation. This architecture can subsequently be combined with backend level testing encoding to form a complete compression sensor