Title :
Design of the scheduler for the high-capacity non-blocking packet switch
Author :
M. Petrovic;A. Smiljanic
Author_Institution :
Belgrade Univ., Serbia
fDate :
6/28/1905 12:00:00 AM
Abstract :
The sequential greedy scheduling (SGS) is a scalable maximal matching algorithm that provides non-blocking in a packet switch with input buffers and a cross-bar. In this paper, we propose the design of the SGS scheduler, and present its FPGA implementation. We examine different design options and measure these implementations in terms of their scalability and speed. It will be shown that multiple input modules of a terabit packet switch can be implemented on one low-cost FPGA device and that the processing can be performed within desired time slot duration
Keywords :
"Packet switching","Switches","Delay","Pipelines","Bandwidth","Scheduling algorithm","Field programmable gate arrays","Processor scheduling","Velocity measurement","Scalability"
Conference_Titel :
High Performance Switching and Routing, 2006 Workshop on
Print_ISBN :
0-7803-9569-7
DOI :
10.1109/HPSR.2006.1709742